1. Field of the Invention
The present invention is related to a phase-locked oscillator circuit which provides a stable output signal synchronized to the phase of an input signal.
2. Description of the Related Art
In synchronous multiplexed transmission systems, a known method of network synchronization is that in which a highly stable clock signal is transmitted from the master station to a slave station, this clock signal being then transmitted from the slave station to other slave stations, each of the slave stations generating a clock signal which is phase-locked to the received clock signal, the generated clock signal being used to perform transmission processing.
Therefore, at each of the slave stations it is necessary to suppress the jitter of the clock signal received via the transmission path, and to generate a stabilized clock signal. For example, in a system which uses a ultra-precise network-synchronization equipment, because there is only a minute variation in phase, a configuration for generating a clock signal using a phase-locked oscillator circuit having a narrow loop bandwidth implemented by a microprocessor or other means is known. In contrast to this, in a configuration in which the master station has a clock generator which is of relatively high stability but not ultra-precise, wherein the clock signal from this clock generator is transmitted to the slave stations, each of the slave stations must have a phase-locked oscillator circuit having a wide pull-in frequency range. In addition, to achieve compactness in the slave stations, it is necessary to make the configuration used to generate such clock signals compact as well.
FIG. 8 shows an example of prior art, in which 81 is a phase-comparison circuit, 82 is a loop filter, 83 is a voltage-controlled oscillator (VCO), 84 is a frequency-conversion circuit, 85 is an M/M+1 frequency divider (hereinafter, referred to as a programmable-ratio frequency-division circuit), 86 is a frequency divider, and 87 is an AND circuit, and wherein frequency conversion is performed by frequency-conversion circuit 84 so that the oscillation frequency of voltage-controlled oscillator 83 is the same as the frequency of the input signal, and phase comparison is performed at phase-comparison circuit 81, the phase-comparison output signal passing through loop filter 82 to serve as the control voltage for voltage-controlled oscillator 83, so that an output signal locked to the phase of the input signal is obtained. By using the received clock signal as this input signal, it is possible to generate a phase-locked clock signal.
The frequency-conversion circuit 84 of this phase-locked oscillator circuit has M/M+1 frequency divider 85, the division ratio of which is switched between M and M+1, frequency divider 86 which controls the switching of this frequency divider, and AND circuit 87, and when the oscillation frequency of voltage-controlled oscillator 83 is not in integer relationship with the input signal frequency, the oscillation frequency of voltage-controlled oscillator 83 is converted so as to be the same as the input signal frequency. For example, if the oscillation frequency of voltage-controlled oscillator 83 is 51.84 MHz and the received signal frequency is 1.544 MHz, M=33, so that M/M+1 frequency divider 85 divides frequency by 33 and 34, the result being 13 divisions by 34 with respect to 10 divisions by 33, so that the 51.84 MHz is frequency converted to 1.544 MHz.
To implement a phase-locked oscillator circuit having high frequency stability, it is necessary to make the loop bandwidth narrow, and also to make the loop gain small, in order to eliminate the influence of input signal variations occurring because of the transmission path and other factors. However, if the loop bandwidth is made narrow and the loop gain is made small, the frequency-tracking characteristics worsen, so that a large variation in input signal frequency causes loss of locking. That is, it becomes impossible to achieve a phase-locked oscillator circuit having a wide locking-on frequency range.
One approach to solving this problem is that of maintaining a narrow loop bandwidth and making the loop gain large. However, doing this results in a worsening of the damping factor, which results in a decrease in the stability of the output signal frequency. If, on the other hand, the loop bandwidth is broadened, although the locking-on frequency range is broadened, tracking of even minute variations in input signal frequency occurs, making it impossible to achieve a phase-locked oscillator circuit with high stability. That is, the phase-locked oscillator circuit exhibits mutually exclusive characteristics, making it impossible with previous examples of phase-locked oscillator circuits to achieve both a broad locking-on frequency range and high stability.
For example, in a synchronous multiplexed transmission system such as mentioned previously, it is desirable to have a phase-locked oscillator circuit that not only has performance such as a locking-on frequency range of .+-.20 ppm, short-term stability of 5.times.10.sup.-9 seconds per second, jitter immunity of 1.5 UI (unit intervals), and frequency of 10 to 150 Hz, but is compact as well.